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The recent evolution of digital technology has resulted in the design of digital processors with increasingly complex capabilities. The implementation of hardware/software co-design methodologies provides new opportunities for the development of low power, high speed DSPs and processor networks. Dedicated digital processors are digital processors with an application specific computational task.

Dedicated Digital Processors presents an integrated and accessible approach to digital processor design principles, processes, and implementations based upon the author's considerable experience in teaching digital systems design and digital signal processing. Emphasis is placed on presentation of hardware/software co-design methods, with examples and illustrations provided throughout the text. System-on-a-chip and embedded systems are described and examples of high speed real-time processing are given. Coverage of standard and emerging DSP architectures enable the reader to make an informed selection when undertaking their own designs.

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This book constitutes the refereed proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems, CHES'99, held in Worcester, MA, USA in August 1999. The 27 revised papers presented together with three invited contributions were carefully reviewed and selected from 42 submissions. The papers are organized in sections on cryptographic hardware, hardware architectures, smartcards and embedded systems, arithmetic algorithms, power attacks, true random numbers, cryptographic algorithms on FPGAs, elliptic curve implementations, new cryptographic schemes and modes of operation. ... Read more

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Network processing units (NPUs) will be the occasion of sweeping changes in the network hardware industry over the next few years. This new breed of microchip impacts chip designers like Intel, equipment vendors like Cisco, application developers like IBM and Morotola, and an army of software engineers who spent the last decade working on protocols and network management solutions. A thoroughly practical dissection of the early NPU market, this designer's guide explains how network processors work and provides detailed information on all major commercial architectures, from features to design considerations. Comparative tables are a rich source of cross-industry info. Coverage includes traffic managers, classification chips, content-addressable memories, switch fabrics, security accelerators, storage coprocessors and NetASICs. ... Read more

Customer Reviews (4)

Astoundingly good book. Comprehensive treatment with real-world views
Every reader buys a book with different expectations and therefore I respect the points made by several other reviewers. For me however, this is one of the best books I've come across in the last decade. I've written two books myself and so I can be reasonably critical. At the same time, everyone has their unique preferences. For mine, this book is tremendous. The author clearly poured his heart into it-- it is one of the most comprehensive books on any subject I've come across. Several things make this book unique. First, the author provides his real perspectives and true opinions on network processors, vendors, approaches, what works, and what doesn't. His years of experience are reflected in the book. He also comments on the industry. He does these things without any pretense of political correctness-- he says it like he sees it. You'll also find him providing his views on deeper technical subjects. He's also perfectly happy to provide those views without giving you a treatise on everyone of the topics he comments on. I like that. He clearly set his sights on giving you as much information as he could in one book. Others may prefer more of a straight textbook like buildup of the material with no change from that theme and coverage only of topics that are built-up from scratch. There is however a large amount of buildup in the book, I just didn't buy it strictly for that. The book covers so much ground that in the 400+ pages the publisher had to reduce the font to keep the book size down. The book not only comments on particular example vendor implementations but also looks at architectural topics. He for example talks about the issues associated with software development environments and the economic tradeoffs an NPU vendor makes in investing in sample code versus a true software development environment. He covers deeper topics such as classification and also includes a chapter on security processors.

disorder of descriptions
I am a embeded linux programmer who want to make a chassis that processing ethernet packets. At that point of view, the contents is insufficient and disorder of descriptions. Hard to understand.

Extremely helpful!
Knowing traditional CPU architectures and their limitations and being confronted with the need to understand how one can tackle numerous network communication protocols in real time under gigabits per seconds data rates, I picked up this book as the only one (to my knowledge) available, which did not seem devoted to esoteric & narrow research of issues. It seemed like a book, which would explain to me the whole landscape of what is needed to make fast equipment work, in other words the big picture. I was completely and positively astounded at the sheer breadth and depth of information that this book conveys. Maybe a better title should be "network processing chips" as it discusses much more than network processors and rigthfully so. The book covers all the necessary components one needs to put together next to a network processor as a big jigsaw puzzle in order to build a powerful working system, e.g. things like switch fabrics, traffic managers, content addressable memory, security coprocessors, etc. The style is flowing and engaging and the structure is very modular so one can go back and forth delving into one's areas of interest. The book can be read either from cover to cover or as a reference. Its binding makes the book even more of a pleasure to use. One must of course be able to understand some basics in order to be able to grasp the content as it may not be "bedtime" reading for some readers; it is fair however to say that after reading it one should have an infinitely better appreciation of how fast routers, wireless switches, etc. have to be logically structured and designed in order to be able to handle all of the quality-of-service-sensitive multimedia traffic they are more and more seeing. A couple of the many companies whose innovative platforms are discussed, have been either acquired or gone out of business for lack of funds during the last couple of years, something not surprising as the market for network processing chips is growing while still getting consolidated. The technology fundamentals however are crystal clear and unalterable. The overall subject is truly vast and each chapter could very well be a book by itself. Nevertheless in my opinion, the author did an excellent job in capturing the overall landscape and in laying out the fundamentals in a fresh way that not only is not intimidating but also makes sense especially for a newcomer. From here one can expand into any direction one wants while being fluent with the terms used in this field. If you want to understand this new area of advanced networking hardware and architecture internals and maybe catch your networking vendor's salesforce a bit off guard, you have simply got to buy this book.

Plenty of useful details, but could be clearer and focused
I read 'Network Processors' to learn more about this relatively new technology that is changing the way network security appliances are designed and deployed.Panos Lekkas' work seemed like the only book available that presented a broad, multi-vendor sweep of the network processor landscape.While the book has plenty of information to offer, I found it did not really live up to my expectations.

Network processors are specialized computing chips built for high performance packet processing applications.I hoped 'Network Processors' would spend a good amount of time making the case for this technology, explaining why NPs are indispensable compared to general purpose CPUs.Unfortunately, I felt the book did not make a compelling case.Chapter 2, titled 'Network Processors: Justification,' is only 10 pages, with a single chart graphing bandwidth demand vs time.I would have liked to see head-to-head comparisons of NPs against CPUs for various network applications.The book spends a lot of time discussing technologies and concepts at the periphery of NPs; I think some of that space could have been put to better use.

Here is an example of why I felt let down by this book.In the preface, the author seems to assure the reader that he will answer questions others tend to ignore.On p. xix the author writes 'In numerous industry discussions, I have encountered experienced software engineers who have implemented cutting-edge protocols, but have no idea what concepts such as scheduling, backpressure, switching fabrics, and classification mean.'To be fair, the author does explain switching fabrics and classification.However, he says almost nothing about backpressure, and he certainly never explicitly defines it; the only mention is on p. 274.

Elsewhere, I thought the book was unnecessarily confusing.It's fine to cover deep technical details, but it helps to start with clear general definitions and progress to more difficult material.The following excerpt from p. 220, the second page of chapter 12, serves as part of the 'introduction' to content addressable memory: 'The principle of associative memory is based on the inverse mechanism of establishing a relationship between the input and a specific piece of information stored in the memory array.'This sentence is fine if the reader knows what 'associative memory' is, understands the 'inverse mechanism,' and can relate to 'the input' and a 'memory array.'

The layout of the book itself may have contributed to my difficulty with it.The font is one of the smallest I have ever encountered.The footnotes are so small as to be almost illegible.I like the hardcover binding, though.

Although not the author's fault, readers should be aware that many of the companies and some of the technologies in 'Network Processors' have disappeared.Each time I encountered a new company or product I checked to see if their Web page or product line still existed.For example, IBM's PowerNP receives an entire chapter; it was sold to Hifn in January 2004.In many cases, however, surviving vendors have not brought too many products to market since the book's late 2002 publication date.

I believe a second edition of 'Network Processors' would benefit from an editor who challenges the author to be more organized and generous with his audience.The book was built on a good idea -- bringing knowledge of NPs to general readers.A second edition should ensure that goal is met, since we do need to know more about this promising technology. ... Read more

Product Description
This digital document is an article from Computer User, published by MSP Communications on October 1, 2000. The length of the article is 2690 words. The page length shown above is based on a typical 300-word page. The article is delivered in HTML format and is available in your Amazon.com Digital Locker immediately after purchase. You can view it with any web browser.

Citation Details
Title: CHIP FIGHT!(AMD's Duron processor vs Intel's Celeron)(Hardware Review)(Evaluation)
Author: Cheryl Masse
Publication: Computer User (Magazine/Journal)
Date: October 1, 2000
Publisher: MSP Communications
Volume: 18Issue: 12Page: 29

Article Type: Evaluation, Product/Service Evaluation

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The purpose of this book is to survey the state of the art and evolving directions in post-silicon and runtime verification. The authors start by giving an overview of the state of the art in verification, particularly current post-silicon methodologies in use in the industry, both for the domain of processor pipeline design and for memory subsystems. They then dive into the presentation of several new post-silicon verification solutions aimed at boosting the verification coverage of modern processors, dedicating several chapters to this topic. The presentation of runtime verification solutions follows a similar approach. This is an area of processor design that is still in its early stages of exploration and that holds the promise of accomplishing the ultimate goal of achieving complete correctness guarantees for microprocessor-based computation. The authors conclude the book with a look towards the future of late-stage verification and its growing role in the processor life-cycle.

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This book is a collection of the finalized versions of the papers presented at the third Eurographics Workshop on Graphics Hardware. The diversity of the contributions reflects the widening range of options for graphics hardware that can be exploited due to the constant evolution of VLSI and software technologies. The first part of the book deals with the algorithmic aspects of graphics systems in a hardware-oriented context. Topics are: VLSI design strategies, data distribution for ray-tracing, the advantages of point-driven image generation with respect to VLSI implementation, use of memory and ease of parallelization, ray-tracing, and image reconstruction. The second part is on specific hardware, on content addressable memories and voxel-based systems. The third part addresses parallel systems: massively parallel object-based architectures, two systems in which image generated by individual rendering systems are composited, a transputer-based parallel display processor. ... Read more

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This digital document is an article from Plastics Engineering, published by Society of Plastics Engineers, Inc. on October 1, 2002. The length of the article is 727 words. The page length shown above is based on a typical 300-word page. The article is delivered in HTML format and is available in your Amazon.com Digital Locker immediately after purchase. You can view it with any web browser.

Citation Details
Title: ERP Software for plastics processors. (Computer Hardware & Software).
Author: Hope Molinaro
Publication: Plastics Engineering (Refereed)
Date: October 1, 2002
Publisher: Society of Plastics Engineers, Inc.
Volume: 58Issue: 10Page: 44(1)

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This digital document is an article from Plastics Engineering, published by Society of Plastics Engineers, Inc. on October 1, 2003. The length of the article is 417 words. The page length shown above is based on a typical 300-word page. The article is delivered in HTML format and is available in your Amazon.com Digital Locker immediately after purchase. You can view it with any web browser.

Citation Details
Title: ERP software for processors.(Computer Hardware & Software)
Author: Hope Molinaro
Publication: Plastics Engineering (Refereed)
Date: October 1, 2003
Publisher: Society of Plastics Engineers, Inc.
Volume: 59Issue: 10Page: 38(1)

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The art of transforming a circuit idea into a chip has changed permanently. Formerly, the electrical, physical and geometrical tasks were predominant. Later, mainly net lists of gates had to be constructed. Nowadays, hardware description languages (HDL) similar to programming languages are central to digital circuit design. HDL-based design is the main subject of this book.
After emphasizing the economic importance of chip design as a key technology, the book deals with VLSI design (Very Large Scale Integration), the design of modern RISC processors, the hardware description language VERILOG, and typical modeling techniques. Numerous examples as well as a VERILOG training simulator are included on a disk. ... Read more

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This volume is devoted to the theoretical foundations of hardware design. The 12 chapters presented are organized in sections on mathematical foundations of hardware modelling; models of hardware and dynamical systems; and verification and deductive design of systems. The book is a memoir documenting scientific work done by the NADA Working Group within ESPRIT Basic Research Action 8533. The chapters address theoretical topics including stream processing, spatially extended systems, hierarchical structures, and integration of digital analogue models. There are case studies of superscalar processors, the Java Virtual Machine, and biological excitable media; various design and verification techniques are presented. ... Read more

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In recent years embedded systems have gained a widespread diffusion both in every market; anyone of us get in touch with them several times a day. Often even without noticing them.Power dissipation, difficulties in increasing the clock frequency, and the need for technology reuse to reduce time-to-market push towards new solutions, such as exploiting inherent application parallelism, running them on multiple standard processor cores.This brought to the definition of Multi-Processor System-on-Chip (MPSoC). Their design raises new challenges due to the large design space and tight design and time-to-market constraints.MPSoC are complex devices and therefore require some particular modeling techniques in order to hide their inherent complexity, without loosing in model accuracy and flexibility.This work approaches two different aspects of MPSoCs design. This is intended to provide an overview of concerns and a comparison with the specific literature of the different fields involved and, at the same time, simplifying the overall MPSoC design problem considering it separately. ... Read more

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This digital document is an article from PC Business Products, published by Worldwide Videotex on June 1, 2002. The length of the article is 851 words. The page length shown above is based on a typical 300-word page. The article is delivered in HTML format and is available in your Amazon.com Digital Locker immediately after purchase. You can view it with any web browser.

Citation Details
Title: GATEWAY ENHANCES NOTEBOOKS W/ MOBILE INTEL PENTIUM 4 PROCESSOR.(Product Announcement)
Publication: PC Business Products (Newsletter)
Date: June 1, 2002
Publisher: Worldwide Videotex
Volume: 14Issue: 6Page: NA

Article Type: Product Announcement

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This digital document is an article from Federal Computer Market Report, published by Millin Publishing, Inc. on May 12, 2003. The length of the article is 535 words. The page length shown above is based on a typical 300-word page. The article is delivered in HTML format and is available in your Amazon.com Digital Locker immediately after purchase. You can view it with any web browser.

Citation Details
Title: Cisco announces intelligent processor engine for the WAN edge.(Cisco NPE-G100)
Publication: Federal Computer Market Report (Newsletter)
Date: May 12, 2003
Publisher: Millin Publishing, Inc.
Volume: 27Issue: 9Page: 8

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Chapters: Pdp-11, Programmed Data Processor, Pdp-8, Dot Matrix Printer, Pdp-10, Pdp-7, Linc, Foonly, Decsystem-20, Vt100, Star Coupler, Decstation, Alphaserver, Dec 7000/10000 Axp, Decserver, Microvax, Vax 8000, Dec 3000 Axp, Vaxstation, Alphastation, Turbochannel, Rainbow 100, Digital Linear Tape, Vaxft, Linc-8, Vax 4000, Dec 4000 Axp, Decpc Axp 150, Vax 6000, Dec Firefly, Q-Bus, Pdp-6, Digital Personal Workstation, Dectape, Dec Multia, Vax 9000, Vt52, Decmate, Dec Professional, Massbus, List of Vax Computers, Firefly Protocol, Rk05, Vax 7000/10000, Unibus, Lk201, Vax-11, Ixp1200, Dectalk, Ra90, Vaxbi Bus, Vt220, Vt05, Mass Storage Control Protocol, Vaxmate, Itsy Pocket Computer, Block-Transfer Instruction, Vaxserver, Vt420, Flip Chip, Vt180, Lk421, Dec Gt40, Palcode, Tu81, Vt500, Jupiter Project, Decsa, System Building Blocks, Synchronous Backplane Interconnect, Digital Storage Systems Interconnect, Standard Drive Interconnect. Source: Wikipedia. Pages: 359. Not illustrated. Free updates online. Purchase includes a free trial membership in the publisher's book club where you can select from more than a million books without charge. Excerpt: The 12-bit PDP-8 was the first successful commercial minicomputer, produced by Digital Equipment Corporation (DEC) in the 1960s. DEC introduced it on 22 March 1965, and sold more than 50,000 systems, the most of any computer up to that date. It was the first widely sold computer in the DEC PDP series of computers (the PDP-5 was not originally intended to be a general-purpose computer). The earliest PDP-8 model (informally known as a "Straight-8") used diode-transistor logic, packaged on flip chip cards, and was about the size of a minibar-fridge. This was followed by the PDP-8/S, a desktop model. By using a one-bit serial ALU implementation, the PDP-8/S was smaller, less expensive, but vastly slower than the original PDP-8. Later systems (the PDP-8/I and /L, the PDP-8/E, /F, and /M, and ...More: http://booksllc.net/?id=24364 ... Read more

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This digital document is an article from Software Industry Report, published by Millin Publishing, Inc. on May 20, 2002. The length of the article is 503 words. The page length shown above is based on a typical 300-word page. The article is delivered in HTML format and is available in your Amazon.com Digital Locker immediately after purchase. You can view it with any web browser.

Citation Details
Title: CISCO ANNOUNCES THE CISCO ADVANCED ATM MULTISERVICE PORTFOLIO.(Cisco Systems MGX 8950, MGX 8830 and Cisco Route Processor Module XF)(Product Announcement)
Publication: Software Industry Report (Newsletter)
Date: May 20, 2002
Publisher: Millin Publishing, Inc.
Volume: 34Issue: 10Page: 8

Article Type: Product Announcement

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